Hi,
Sasken opens up a world of opportunities for professionals with 1 to 8 years of experience in the skills mentioned below.
Date 3rd and 4th July 2010 in Chennai
Time Starting at 9:30 AM
Venue Sasken Communication Technologies Ltd,Unit No 702,7th Floor
Campus 3B, RMZ Millenia Business Park, 143
Dr M G R Road, Kandanchavady
Chennai 600 096
You can ask all your friends with the desired qualifications and skill sets to walk in directly to the above mentioned venue on 3rd and 4th July 2010
System Verilog / Specman Verification Engineer (Exp: 0.5 to 8 Yrs) (Job Location : Bangalore / Noida)
• BFMs Development, Test case development, Module and SOC level verification.
SoC Level Physical Designer (Exp: 0.5 to 8 Yrs) (Job Location : Bangalore)
• Place & Route(PnR),CTS, Floor Planning, Timing closure, Power Planning, IO planning
Synthesis, STA, MAGMA, ICC, Primetime, PTSI, Design Compiler, Apache, Calibre.
DFT Engineer (Exp: 0.5 to 8 Yrs) (Job Location : Bangalore)
• Strong knowledge of DFT including JTAG, MBIST, scan, on-chip scan compression,Fault models, ATPG and fault simulation and AC scan for at speed testing
Analog Layout Requirement: (2-5 yrs.) (Job Location : Bangalore / Pune)
• Handling Analog modules like DAC, ADC , Reference , LDO , LCD with good knowledge of ESD and shielding requirements Knowledge of mixed signal full-chip requirements desired .
• Tools : Cadence Virtuoso , Cadence Schematic composer , Assura / Calibre DRC/LVS/Antenna , parasitic extraction.
Please Note:
• Candidates who have already taken the test or interview in last 3 months and fresher need not attend this walk-in.
The ideal profile for the below mentioned openings would be Engineering Graduates, Post Graduates
Sasken opens up a world of opportunities for professionals with 1 to 8 years of experience in the skills mentioned below.
Date 3rd and 4th July 2010 in Chennai
Time Starting at 9:30 AM
Venue Sasken Communication Technologies Ltd,Unit No 702,7th Floor
Campus 3B, RMZ Millenia Business Park, 143
Dr M G R Road, Kandanchavady
Chennai 600 096
You can ask all your friends with the desired qualifications and skill sets to walk in directly to the above mentioned venue on 3rd and 4th July 2010
System Verilog / Specman Verification Engineer (Exp: 0.5 to 8 Yrs) (Job Location : Bangalore / Noida)
• BFMs Development, Test case development, Module and SOC level verification.
SoC Level Physical Designer (Exp: 0.5 to 8 Yrs) (Job Location : Bangalore)
• Place & Route(PnR),CTS, Floor Planning, Timing closure, Power Planning, IO planning
Synthesis, STA, MAGMA, ICC, Primetime, PTSI, Design Compiler, Apache, Calibre.
DFT Engineer (Exp: 0.5 to 8 Yrs) (Job Location : Bangalore)
• Strong knowledge of DFT including JTAG, MBIST, scan, on-chip scan compression,Fault models, ATPG and fault simulation and AC scan for at speed testing
Analog Layout Requirement: (2-5 yrs.) (Job Location : Bangalore / Pune)
• Handling Analog modules like DAC, ADC , Reference , LDO , LCD with good knowledge of ESD and shielding requirements Knowledge of mixed signal full-chip requirements desired .
• Tools : Cadence Virtuoso , Cadence Schematic composer , Assura / Calibre DRC/LVS/Antenna , parasitic extraction.
Please Note:
• Candidates who have already taken the test or interview in last 3 months and fresher need not attend this walk-in.
The ideal profile for the below mentioned openings would be Engineering Graduates, Post Graduates