Career Search

Custom Search

500 Opening for VLSI Professional

send u r CV to hafsal4u2u@gmail.com

500 Opening for VLSI Professional In bangalore/Pune /Hyderabad /Cochin
Following are the Openings for 5th Largest Vlsi Company in world.
If your skills sets matches with any of the following requirement

JD for STA profiles
---
- Worked on timing closure
- Sound understanding of constraints
- Understand the various check to be done on closure of blocks (post Layout STA)
- Good communication (oral/Written)
- Understands the DFT concepts

Vlsi Designers

Design of medium complex blocks
Responsible for RTL coding and unit level verification
Integration of block level RTL to top level RTL code
Synthesis of the developed RTL code
Knowledge basics of ASIC DFT
Hands-on experience in RTL coding
Experienced in Verilog/VHDL coding,
Experience in Unix environment
Tools: Simulators, Design Compiler (Preferred)
Experience in at least one Bus protocol
Candidate should have experience in RTL design using Verilog/ VHDL. Should have worked in medium complex block level design, running regression and debugging of issues. Should possess good hands-on in the usage of simulation tools like VCS/Modelsim/NCSim and design compiler (or similar tools) for synthesis. Should possess good analytical and problem solving skills. Good documentation skills and good communication skills are a must. Self-driven person with ability to work in a fast-paced environment.

Vlsi Verification
Verification of medium complex blocks
Responsible for Testbench development for unit level level verification
Test component development such as drivers, checkers, monitors
Integration of 3rd Party Verification IPs into the testbench
Testcase development
Testcase execution, simulation and debugging
Performing coverage analysis and regressions
Netlist simulations
Hands-on experience in using Verilog for verification and exposure to any HVL,
Experienced in Verilog/VHDL coding,
Experience in Unix environment for verification
Tools: VCS,Modelsim,NCSIM
Knowledge of Functional coverage
Scripting languages like Perl/Shell scripting
Experience in at least one Bus protocol

Physical Design

The job involves physical design activities, which includes Physical Design & electrical/reliability analysis for variant SoCs, ASIC for various applications, in lead role. Traditionally called ASIC backend includes Timing Closure and/or Physical Design & electrical/reliability analysis. รข€¢Must be able to demonstrate thorough knowledge of physical design concept from anything ranging from RTL to Tapeout.
Experience in Synopsys ICC/ BlastFusion / Talus / SoC Encounter / Astro or equivalent, and Blast plan pro / FE or equivalent is a must. Experience on complex SoCs is recommended. Good understanding of basic electronics circuit design principles. Strong analytical and engineering problem solving skills (including Logic design and analysis). Strong knowledge of VLSI design, layout and ASIC design flow. Should have worked in challenging projects involving 90nm and/or 65nm. Should have a sound understanding of Deep-Sub-Micron effects. In-depth understanding of timing issues in gate-level and transistor-level logic designs. Should also have very good understanding of logic synthesis. Experience with Synopsys, Magma and/or cadence tools. Gone through few tape-outs The ability to build production-quality flow automation and provide effective customer support. Should have led teams in many of the following areas.

Synthesis
Floorplanning/IO/Package Planning
Place and Route
Timing / Noise / Design Closure.
Software skills preferred are ability to write/debug PERL, TCL, and shell scripts. Experience with the UNIX operating system is required.

DFT
Working Exp on ATPG,SCAN,JTAG, MBIST.
Should be able to DFT task planning
Good Communication Skills
Exp in any of any theses Fastscan /TestKompress /LBIST (not mandatoray)
Well versed with technical skills sets.

If your skill sets matches with any of the above mentioned skill sets
Total Exp
Rel Exp
Current Organisation
E-Mail ID
Alternate E mail ID
DOB
Total exp
Education
Year of Education completed
Current CTC
Exp CTC
Interview location Bangalore /Pune /Hyderabad /Cochin
Kindly forward this mail to your colleagues if they are looking for change