Find the below two requirement for Memory-Design/Characterization Engineer with my contact details.
Contact: Mahendra
Mobile: 9980278762
For Positon: Memory layout Engineer
Experience: 1-10 years
Location: Bangalore
Company: Interra Systems
Layout editing and debugging skills
Physical verification (LVS, antenna, DFM). Experiences with Synopsys/Mentor verification tools are desirable.
Should have worked on 90nm technology
Experience on memories
Knowledge of scripting Perl and Skill are desirable
For Position: Memory-Design/Characterization Engineer
Job Description:
1.Design and development of memory compilers / register files.
2.Responsible for circuit design, generation and verification of memory models.
3.To be good team player.
Required Skill set:
1. Minimum 3 years experience in memory circuit design and / or characterization.
2. Experience in circuit simulation, debugging, and characterization
3. Experience in generation, verification and validation of frontend memory models รข€" timing views, verilog /vhdl /tetramax /CPF /CPF
4. Good understanding in release procedures and QA process of memory models.
5. Understanding of layout guidelines, DFM and technology tradeoffs in 65nm/45nm/28nm processes.
6. Good documentation, communication and presentation skills.
Regards,
Mahendra
Contact: Mahendra
Mobile: 9980278762
For Positon: Memory layout Engineer
Experience: 1-10 years
Location: Bangalore
Company: Interra Systems
Layout editing and debugging skills
Physical verification (LVS, antenna, DFM). Experiences with Synopsys/Mentor verification tools are desirable.
Should have worked on 90nm technology
Experience on memories
Knowledge of scripting Perl and Skill are desirable
For Position: Memory-Design/Characterization Engineer
Job Description:
1.Design and development of memory compilers / register files.
2.Responsible for circuit design, generation and verification of memory models.
3.To be good team player.
Required Skill set:
1. Minimum 3 years experience in memory circuit design and / or characterization.
2. Experience in circuit simulation, debugging, and characterization
3. Experience in generation, verification and validation of frontend memory models รข€" timing views, verilog /vhdl /tetramax /CPF /CPF
4. Good understanding in release procedures and QA process of memory models.
5. Understanding of layout guidelines, DFM and technology tradeoffs in 65nm/45nm/28nm processes.
6. Good documentation, communication and presentation skills.
Regards,
Mahendra
