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AMD/Mentor Graphics/Atrenta/Freescale/ACtel/Qlogic/Open silicon/_NOIDA_Bang_HYD_Pune


Dear Candidate,

HI………….
Good day you

W have Openings at

AMD Bangalore/HYD_____Any verification_3-20yrs Upto SOC Verification manager ROle
• Actel Hyderabad____--- Hands on project experience with leading edge verification methodologies like OVM/VMM/e(Specman)
• Hands on project experience in verification projects using OVM/VMM/e(Specman)
• Exposure to protocols like PCIe, AMBA, and DDR1/2/3
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OPensilicon Bangalore/Pune
) Sr IP Applications Engineer, Bangalore, India
Min Educational Qualifications: Bachelor’s degree or equivalent in Electronics Engineering, Computer Science, or closely related field.Relevant Experience: 5-8 years of experience in ASIC Design, including the design and integration of various types of IP, such as embedded memories, IOs, analog, PHY/Serdes (e.g. DDR, USB, PCIe, XAUI, SATA) and soft-IP (embedded CPUs and associated SoC fabric).




Job Description:
• Perform and support the design integration of both digital and analog embedded IP such as CPUs (e.g. ARM/MIPS/ARC/Tensilica), PHY/Serdes (e.g. DDR, USB, PCIe, XAUI, SATA) embedded memory, IOs and analog IP
• Work directly with customers to propose the optimal IP solution which meets their ASIC requirements
• Work closely with IP Vendors to ensure their IP meets the ASIC’s requirements
• Provide product and technical support to both the marketing/sales and physical design organizations
Requirements:
• 4-8 years of experience in IP Applications engineering or IC Design is a must.
• Experience with Front and Back-end (including HSPICE) tools from Cadence/Synopsys is a must.
• Excellent verbal and written communication skills
• A deep understanding of IP design and IP integration related issues.
• Experience in the application of 3rd-party IP in ASIC design and the associated issues of selection, qualification, integration and support
• Experience in customer-facing roles is desired, preferably applications engineering





QLOGIC Bangalore PUNE
• BS or MS or equivalent degree in Electrical Engineering, Computer Engineering or related discipline with 5 to 12 years of experience
• Experience developing and using system or block level complex test benches as well as writing verification plans and requirements
• Experience implementing directed and random test cases
• Must have experience with Verilog, System Verilog, code and functional coverage. (OVM/VMM/Formal Verification experience would be a plus.)
• Excellent written & verbal communications skills
• Experience with industry standard protocol. (PCI Express or Ethernet would be a plus


Mentor Graphics NOIDA

Job Responsibilities:
Be an integral part of a team that is developing verification IPs such as PCIe, USB3, 100 Gigabit Ethernet and AMBA bus protocols for use with Questa RTL simulation.
Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques.
You will specify, implement, test, and manage regression tests of these IPs for a wide range of end user applications. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.

Job Requirements:
• Solid Verilog HDL RTL knowledge
• Solid RTL simulation and test bench experience
• Intimate knowledge of one or more standard bus protocols
• Solid engineering
• B.Tech/M.Tech in electrical engineering or related field
• 3-5 years of experience in verification engineering

Desired Requirements:
• Experience with cycle-based simulation and constrained-random simulation
• Experience with System Verilog or System C
• Knowledge of assertion languages such as SVA, PSL
• Experience with Formal Property Verification tools

Other Requirements:
Bus Protocol know how with SV, OVM, UVM, VMM, Specman knowhow etc.

Freescale - Noida

Job Description:-

Verification Engineer/Sr. Engineer/Lead
Job Location - Noida
Job Opportunity: Seeking highly motivated, energetic, team-oriented Engineer/Lead willing to take the challenge of delivering the first pass success of complex microcontroller based SoCs and IPs using the latest advanced verification languages and methodology.
The Verification Engineer/Lead would be working with experienced and motivated team of Systems, Physical design, DFT, Mixed Signal and other local/remote teams to address the verification challenges in the context of the block, chip, and overall system, through the use of simulation, hardware modeling, formal verification and active participation in pre/post silicon validation.

Key Responsibilities
• Evaluate and deploy the evolving verification methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules.
• Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes and recommend and implement the process improvements to ensure ‘Zero Defect’ chips
• Encouraging and influencing technological innovations in the team
• Effectively manage highly energetic and intellectual team members through coaching and mentoring, provide technical direction to team members on project issues, and provide guidance and career planning to team members.
• Ensure that SMART metrics are established to measure the Design Verification processes and goals.
• Ability to work well as part of a team both locally, and also with remote or multi-site teams

Key Skills
• Self starter with 3-10 years of experience on SOC/Chip level/Cluster/IP verification on multimillion Gate and complex Design with multiple clocks and power domains with minimal supervision
• Testbench and Testplan development to address Analog/Mixed signal and Testability aspects of the chip along with functional requirements
• Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI, Memory(Flash, SRAM,DDR) and memory controllers
• Experience in automotive protocols like LIN, CAN, Flex, Graphics/Multimedia/Networking protocols like Ethernet, USB, ITU T.656 would be an advantage
• Experience and working knowledge of HVLs (SV/C++/SC/e/VERA), HDLs (Verilog/VHDL),PLI/DPI, simulators (NCSim/ModelSim/Questa/VCS)
• Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management
• Experience in Low power verification using CPF/UPF would be a big plus
• Exposure to pre silicon validation/emulation is an added advantage
• Leadership experience in quality management and quality improvement.