Hi,
Greetings from L&T InfoTech.
Walk-in this Saturday (23rd October'10) with your updated CV and last 3 months pay slip in Chennai Location for the below mentioned requirements.
Education: BE/BTech/MTech/MS/ME
Experience: 2 รข€" 8 years
Location: Chennai & Bangalore
Timings: 9:00 am- 3:00 pm
Requirements:
1. ASIC Implementation: ASIC Synthesis, Formal Verification, STA, Linting, CDC; Tools: Synopsys DC, Mentor 0-in, Spyglass, Cadence LEC
2. ASIC Design: RTL Coding (Verilog), Architecture/MicroArchitecture of ARM based ASICs, Linting, Synthesis/STA, Support to Physical Design Team
3. ASIC Verification: Functional Verification of ARM based ASICs using SystemVerilog/Specman, VMM/OVM/RVM based TestBench Architecture, Assertion based and Functional Coverage Driven Verification, TestPlan extraction, C/Assembly testcases development, Regression and Scripting
4. ASIC Gate Level Simulation Expert, ASIC & GLS or Gate Level simulation & SDF
5. DFT : Expertise in DC/AC tests & on-chip compression techniques, strong pattern simulation and failure debugging experience with/without SDF, must have Synopsys DFT tools experience, pattern conversion tools, JTAG/BIST experience is a plus
Venue Details:
L & T Infotech
TC3, L& T InfoTech Park,
Mount Poonamallie Road,
Manapakkam-Chennai
Contact Person: Ms. Nethra Nagaraj
T: 91- 044 2253 5772
Thanks and Regards
Nethra
Talent Acquisition
L&T Infotech
Bangalore.
