Requirement:
>>Development of IP building blocks and methodologies for Intel's System On Chip (SoC) solutions for the different market segments**.
Qualification :
>>Development of IP building blocks and methodologies for Intel's System On Chip (SoC) solutions for the different market segments**.
Qualification :
- Master of Science (or a Master of Technology) degree in Electrical Engineering with more than ten years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than twelve years of relevant industry experience.
- Relevant ASIC design/validation experience in front end processes including Microarchitecture, RTL development, functional and performance verification
- Expertise in architecture, micro-architecture, design of design blocks (IP) to system-on-chip (SoC) components
- – Experience in one/more of the following system bus interfaces like PCI_Express, USB, SATA, SDIO, MIPI and /or AMBA.
- Knowledge of SVA
- Knowledge of memory controllers, CPU architecture is a plus
- Knowledge of considerations for performance, power and cost optimization is desirable
- Looking for highly motivated individuals and ability to deal with ambiguity
- Good mentoring and leadership skills
- Ability to work in a team environment
- Good debugging and problem solving skills
- Ability to work with external technology companies for combined development of SOCs
- Responsibilities : In this position, the candidate is expected to lead/work with a team of engineers to design the building blocks (soft IPs) for Intel's next generation chips (including SOCs) for the different market segments.
If you fulfill all these conditions then send your CV to prakruthix.g.s@intel.com
